1. Technical Field
This invention relates to non-volatile memory. More specifically, the invention relates to accessing non-volatile memory by a service processor.
2. Description of the Prior Art
Modern computer systems typically have firmware stored in the non-volatile memory. Non-volatile memory is a category of memory that holds their content without electrical power and includes read-only memory (ROM), programmable ROM (PROM), erasable and programmable ROM (EPROM), and electrically erasable and programmable ROM (EEPROM) technologies. The firmware may include the basic input/output system (BIOS) of the computer system. The BIOS is a set of routines in a computer which provides an interface between the operating system and the hardware. Typically, the BIOS supports all peripheral technologies and internal services.
FIG. 1 is a prior art block diagram (10) of a chipset architecture of a sample node of a multinode shared memory multiprocessor system. Such systems offer a common physical memory address space that all processors can access. Multiple processes therein, or multiple threads within a process, can communicate through shared variable in memory because the system allows the processes to read or write to the same memory location in the computer system. Firmware or other non-volatile memory in this chipset architecture is located behind each of two different bridge controllers of the architecture, so that in order to access either of the firmware hubs the process must interface with a controller associated with the respective hub. One of the bridge controllers, commonly referred to as the north bridge controller (22), is the controller for the host bus (20) that interfaces between the system processors (CPUs) (12), (14), and (16) of the multiprocessor system and the north firmware hubs (24), which are known in the art to include high speed components, such as memory, accelerated graphics port bus, and the Peripheral Interconnect (PCI) bus. The other bridge controller, commonly referred to as the south bridge controller (32), stems from the I/O bus (30) and the I/O bridge (26), and is the controller that interfaces the service processor (28) and the south firmware hubs (34), which are known to include Integrated Drive Electronics (IDE) drives and lower speed ports, such as Universal Serial Bus (USB) ports, serial ports, audio ports, etc. Each node in a multi-node computer systems commonly has a service processor (28) that interfaces with the south bridge controller (32). The service processor (28) is also connected to central processing units (12), (14), and (16) via a JTAG bus, also known as an IEEE 1149.1 Standard Test Access Port (18). The service processor (28) is typically responsible for handling maintenance and other service related tasks for its node.
A problem associated with this chipset architecture is that the service processor of a node only has access to system resources located on the south bridge side of the node. The system resources located on the north bridge side of the node are inaccessible to the components located behind the south bridge controller, which prevents the service processor from accessing those resources. Therefore, the service processor cannot maintain the system resources located behind the north bridge controller. This can be problematic in situations where the service processor is responsible for firmware located behind the north bridge controller. In addition, firmware hub interfaces of both the north bridge controller and the south bridge controller may be operating at different speeds based upon requirements of the ports in the associated firmware hubs and controllers. Accordingly, a hardware solution which includes modifying the system architecture to include a multiplexer is required to address the operating speeds of the firmware hubs while enabling communication from the service processor.
One prior art solution, U.S. Patent Publication 2003/0065893 to Lary et al., uses multiplexing hardware incorporated into the chipset architecture to enable firmware access by the service processor. More specifically, this publication has two multiplexers to multiplex the low pin count (LPC) bus clock, and data and control signals using transistors, such as field effect transistors (FETs). The multiplexers are controlled by the service processor and provide access to any desired firmware hub via an accessible firmware hub interface.
However, there are limitations associated with what is disclosed in the Lary et al. publication. For example, it utilizes a hardware solution that requires adding two multiplexers to the chipset architecture, a first multiplexer for a north firmware hub and a second multiplexer for a south firmware hub. There is therefore a need for a software solution to enable the service processor to access the north and south firmware hubs, without the need for a hardware modification to the chipset.